Physical Verification Design Engineer
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.
- Work with FE team to understand chip architecture and drive physical verification aspects early in design cycle.
- Working on full chip DRC, LVS DRC.
- Work with physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support.
- Support partition owners with place and route activities, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
You will have hands on experience in physical design and large chip integration. Familiar with TCL scripting, General partition PD flow - understand how to support partition owners with DRC issues Needs to be familiar with power grid trade offs, IR/IVD Familiar with GDS assembly, GDS requirements for hard macros. Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence. Understanding of DRC correlation with PNR tools, ERC, high voltage checks. Background with LVS. A detailed understanding of database management issues. From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is desirable.
Education & Experience
MSEE or equivalent is required