Physical Design Engineering Lead
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be responsible for leading a physical implementation team from netlist to tapeout.
- Be the main physical design technical interface to cross functional teams
- Plan and track execution, managing risk to tapeout
- Technical leadership, drive team to meet all PPA and design goals on schedule
- Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
- Drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
- Be focal point for place and route, drive the work among PnR engineers, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR.
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
You will have 10+ years of hands on experience in physical design and large chip integration Needs to be familiar with all aspects of ASIC design flows all aspects including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence. You have experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies. A detailed understanding of database management issues will be required From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required. Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Education & Experience
MSEE or equivalent is required