GPU FE Design Implementation Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine working in a team where the only limits are the laws of physics and your imagination. At Apple, great ideas have a way of becoming great products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices. Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.
- We seek highly motivated individuals with design synthesis experience that value crafted RTL design principles and quality physical design implementation.
- Own block level synthesis and drive optimizations using advanced synthesis techniques and RTL design improvement for optimal Area, Timing Power.
- Understand and be willing to collaborate with Physical Design/Timing teams on physical concepts like floor-planning, placement, congestion, and timing constraints.
- Ability to analyze critical paths and help drive closure across Design and Backend teams.
- Experience with using logic equivalence and netlist checks to validate functionality/quality.
- Ability to tackle complex problems across multiple domains.
- Excellent written and verbal communication, exceptional organization skills and ability to work well within multi-discipline teams.
- Relevant scripting experience in ASIC flows - TCL, Perl, Data manipulation.
The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis and optimization of the delivered IP. You will use and develop advanced techniques to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Education & Experience
BSc/MSEE/M Eng/BEng or equivalent is required.
- Additional Qualifications (Preferred, but not required):
- Familiarity with DFT insertion.
- Familiarity with simulation, debugging tools and experience of working closely with design verification team.
- Hands on experience using ECOs for functionality and timing.
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts for RTL and Gate-Level
- Experience working on CPUs, GPUs, or DSPs is desirable.