DRAM Packaging Architect

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number: 200062686
Envision what you could do here. At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight, and inspire millions of Apple’s customers every single day. Summary: Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for perfection to work towards an extraordinary result? We are looking for a hardworking and passionate DRAM Packaging Engineer to join our team. SEG Packaging is a key part of the HW Technologies team, and is located in Cupertino, CA. This team invents, designs, develops and integrates electronic packaging solutions for the Apple’s internal and customized external components of hardware for its consumer electronic products such as iPhone, iPad, Mac pc, Apple Watch, Apple TV, etc. As a DRAM packaging engineer, you will lead the memory package development by managing the external memory vendors and steering their packaging design compatibility to Apple system components (iOS, MacOS platforms). You will partner with the internal SEG teams, defining the memory package architecture, die pad layout, package size, interconnect and package density, and will support the overall system level architecture, product teams and overall program through the development and NPI cycle.

Key Qualifications

  • Working knowledge in Si circuit/DRAM cell design and package design for mobile memory products : LPDRAM, etc
  • Strong working experience in Assembly process development, system level downstream process interaction and packaging inspection metrology for mobile DRAM/MCP memory products
  • Expert in DRAM/MCP die / package layout design/assembly design rule
  • Expert in packaging substrate and assembly process technology, test and reliability
  • Packaging Materials, mechanical and thermal behaviors working knowledge
  • Very good understanding and knowledge in memory SIPI, layout tradeoffs
  • Excellent engineering problem solving skills, with strong engineering physics and data driven analysis
  • Strong written and verbal communication skills

Description

Define the memory package POR (plan of record): Package architecture, technology, process, form factor, layout, bill of materials (BOM), design rules, thermo-mechanical, signal integrity, power integrity Publish internal package specs for customized memory Drive next generation memory Silicon & package architecture and technology roadmap Close partnership with multiple internal teams in HW technologies group supporting weekly and monthly memory technology reviews Establish trusting and collaborative relationship and communication channels, as a direct interface with vendors for DRAM memory package development and qualification Review, drive and approve the DRAM memory vendors DEOs/characterization plans, technology and product qualification and data for package development Drive industry with advanced package processes, new materials and leading edge specifications About 10% international travel required

Education & Experience

Ph.D preferred or MSc (EE, ChemE, ME, Materials Science/Engineering major) with 10+ years of experience in integration in DRAM memory package and/or memory product development.

Additional Requirements