Standard Cell Library Architect and PPA Engineer
Santa Clara Valley (Cupertino), California, United States
Do you want to utilize your engineering background to make big things happen? Do you have a passion for crafting entirely new solutions and love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Standard Cell Design Engineers. In this highly visible role, you will work on Library architecture and PPA of foundation IP in advanced technology nodes.
- We are looking for applicants with 10+ years of relevant experience in Standard Cell Library architecture.
- Technical Leadership.
- Experience in device, transistor and logic level PPA Analysis.
- Expert knowledge of RTL2GDS flows, with UPF.
- Parasitic Extraction with Synopsys StarRC or similar tools.
- Static Timing Analysis with Synopsys Primetime or similar tools.
- Crosstalk analysis, formal verification, EM and power grid analysis.
- ECO generation using Synopsys Primetime or similar tools.
- Physical Verification DRC/LVS/ERC using Mentor Calibre or similar tools.
- Scripting with Shell, Tcl, Perl and/or Python.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As part of Standard Cell Library development, you will perform the following: • Engage with various multi-functional teams to explore next generation library improvements with focus on improving PPA of designs; • Explore innovative library architectures for advanced technology nodes; • Lead PPA (power-performance-area) discussions with CPU/SOC/GPU/AMS physical design teams; • Drive library performance evaluation.
Education & Experience
BSEE / MSEE is required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.