CSM Physical Design Lead
Austin, Texas, United States
The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies! Our team is looking to add a remarkable Physical Design Lead to collaborate with the hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products! We are looking for applicants with 10+ years of experience in the Physical Design of SoCs. This person will have in depth practical knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification. As well as, a proven understanding of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.
- - 5+ years of experience in leading physical design teams.
- - Consistent track record of having taped out a number of complex chips - from gates to GDS.
- - Good knowledge of digital design concepts.
- - Solid understanding of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.
- - Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.
- - Hands-on experience in Power and Signal Integrity analysis.
- - Should have the skills required to debug and fix LVS, DRC, Antenna, ERC issues.
- - Capability to work with multi-functional teams - internal and external and to balance multiple projects concurrently with very ambitious schedules.
- - Strong analytical skills with the ability to prioritize tasks and make critical decisions.
- - Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc.
- - Excellent verbal and written communication skills.
- One or more of the following skills will be an added plus:
- - Mixed signal SoC tapeouts involving multiple instances of analog IPs.
- - Experience in DFT algorithms, memory and logic bist, physical implementation, timing closure, ATPG generation.
- - Low power / leakage management methodology and techniques.
- - Extraction and characterization of IP elements.
- - Experience of collaborating with and leading sub-contractor design houses and silicon vendors.
Imagine yourself at the center of our hardware development effort. Here you will play a strategic role in getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community. In this role, you will be responsible for ensuring the high quality of the chips and expected to: - Audit vendor PD flows and methodologies for any holes and set up issues. - Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips. - Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals. - Collaborate with other teams like the packaging, process etc. to resolve any issues in the project. - Conduct periodic design reviews - with deep technical dives - to make sure the project is on schedule and maintaining a high standard of work. - Review all of the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval. - Provide post tapeout support to work on ECOs and debug, if required. - Have the tenacity to stick to the highest standards and not succumb to pressures to sign-off on anything unless 100% satisfied. - Adhere to a strict and consistent standard of operation and professionalism across all vendors and projects.
Education & Experience
BSEE / MSEE is required, PhD preferred.
- Some Travel Required - Domestic and International.