HardIP Test Engineer
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. We are seeking a dynamic engineer to develop ATE test programs for debug, characterization, qualification and production of SoC devices specializing in HardIP tests.
- In depth knowledge of Semiconductor Manufacturing Process
- Deep understanding of High Speed Digital and Analog circuits, Design for Test and Manufacturing Concepts.
- Expertise in Semiconductor Test Methodology.
- Experience working with Digital, Mixed Signal, SOC Devices with hands on VLSI ATE experience. DFT experience is a plus.
- Strong Programming skills for writing and debugging test programs and HW related issues.
- Competency in programming with Scripting languages (IE., Perl/Python) and high level languages (IE., C/C++ or Visual Basic.)
- Able to work with test equipment (IE., oscilloscope, logic analyzer, etc)
- Experience High Speed Board Design & SI analysis.
- 5+ years meaningful experience
- Travel is required
- Develop and document test plan for new IPs. - Work with DFT and design teams to evaluate IP testability and debug new silicon - Design and debug test SW & HW for Production, Characterization & Reliability. - Bring quality and cost-effective test solution for mass production. - Oversee test related activities with both internal and external group.
Education & Experience
BSEE / MSEE is required