CPU Top Level Verification
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product As a Graphics Triage Engineer you will be responsible for triaging graphics-related silicon failures in a system and resolving root cause of the failure. In this highly visible role, you will be at the center of a chip design effort interfacing with many disciplines, with a critical impact on getting high quality products to millions of customers quickly.
- You should have deep knowledge of verification methodology
- Verification tool and verification development experience
- Strong in C, C++
- Verilog and scripting languages.
- You should be a phenomenal teammate with excellent communication skills, be able to work independently. Knowledge of digital logic design and processor architecture
As a chip verification methodology and tool engineer being responsible for the verification methodology, tools, and flow of a high performance lower power processor design, you will have the responsibilities as follows: - Work closely with verification engineers and RTL designers on defining effective verification methodology for low power complex processor design. - Drive and develop the tools and flows for advanced verification methodology. - Developing, verifying, and maintaining efficient testbench environments - Test the tool flows with selected blocks from the real design - Develop and automate simulation, emulation, and FPGA model build flows
Education & Experience