Pixel IP Design Engineer - Integration
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, forward-thinking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next extraordinary Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the extraordinary and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. In this highly visible role, you will be at the center of a SoC design effort working with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- You will have experience in SoC design
- Previous experience in IP integration into SoC.
- You will have industry exposure to and knowledge of SoC design methodology, especially logic synthesis, static timing analysis, and logic equivalence checking.
- Experience with system design methodologies that contain multiple clock domains.
- Experience in clock, power management and system debug designs a plus.
- Experience in low-power design issues, tools, and methodologies including UPF
- Power intent specification is helpful.
- Strong multi-functional team skills
- Excellent written and verbal communication
As a senior SoC Design/Integration engineer you will have responsibilities spanning all aspects of SoC: You will define uArch specs, create performance modeling, and interact with many multi-functional disciplines. You will help define chip level design infrastructure. Integrate both internal and external IPs. Responsibility includes feasibility, micro-architecture, RTL design, front-end implementation and post-silicon system bring-up.
Education & Experience
MSEE or BSEE Degree, or equivalent is required