Analog Mixed-Signal Verification Lead

San Diego, California, United States


Role Number:200085784
Would you like to join Apple’s growing cellular wireless design team? Do you thrive on pushing the simulation and modeling limits of highly complex RF cellular transceivers SOC in advanced technology nodes? Our team is responsible for all aspects of cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. In this technical, hands-on management role, you will be leading a team in charge of every aspect of a cellular transceiver SOC verification from modeling analog building blocks used in PLLs, ADCs, DACs, RF Receiver and transmitter to pre-silicon RTL verification of communication subsystem including MAC, PHY, interfaces and mixed signal digital controls for PLLs, ADCs and DACs.

Key Qualifications

  • - 10+ years of industry verification experience with RF/Mixed-Signal blocks, RTL Digital Verification for highly integrated transceivers and SOC verification.
  • - Deep understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, parasitic back-annotation, gate level simulation, logic equivalence checking, lower power design flow, etc.
  • - Expertise building Mixed-Signal testbenches, checkers and tests.
  • - Expertise creating and using real-numbered analog behavioral models in SystemVerilog or other language.
  • - Experience in HVL and HDL (SystemVerilog, Verilog)
  • - Experience with one or more of the following is a plus: embedded CPUs, bus fabric (AXI/AHB/APB), DMA, serial interface design (I2C, SPI, UART), wireless protocols, power management, signal processing.
  • - Familiarity with ASIC test methodology and knowledge of techniques such as scan insertion, memory BIST and test pattern generation is required.
  • - Strong verification skills in problem solving, constrained random testing, and debugging.
  • - Good understanding of common analog/RF blocks.
  • - Experience with HVL methodology (UVM/OVM/VMM) a plus.
  • - Experience with signal processing using Python or Matlab a plus.
  • - Experience with Virtuoso Composer, ADE and HED a plus.
  • - Experience with SystemVerilog Assertion (SVA) a plus.
  • - Team spirit, excellent communication skills and demonstrated capability to lead a team to success.


- Take responsibility for all aspects of RF Analog mixed signal employed by the team and ensure the application of uniform standards and adoption of best practices. - Lead the RF AMS verification team and take responsibility for hiring, resource planning, scheduling, performance management, communication with upper management and overall design team execution. - Build block / subsystem / chip level testbench using best in class DV methodology. - Work with RF and modem systems team to understand the top-level requirements of the digital functions and develop detailed specifications. - Review specifications, extract features, define and execute analog mixed signal verification plan. - Develop top/block level RF/ AMS testbenches, and generate directed/ constrained random tests in a UVM framework. - Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks. - Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage. - Write scripts for automation of flow and implement their use. - Help with the generation of test vectors and functional mode vectors.

Education & Experience

BSEE is required. MSEE/PhD is preferred.

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.