Cellular ASIC Integration Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200087181
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? Apple's world-class design and integration processes is driven by top-notch cellular integration engineers who own the integration and development of a wide variety of designs within a chip and can coordinate with internal and external teams to micro-architect, design, verify, release, complete production synthesis, formal verification and timing analysis on the project’s scheduled delivery dates. This is a high-visibility and critical role requiring close working relationships with many other groups.

Key Qualifications

  • This position requires thorough knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation. As a member of this elite team, you must have the following background:
  • At least 5+ years of experience in ASIC design flow.
  • Experience in high performance designs in high volume production for low power applications.
  • Consistent track record of RTL design and timing closure on large complex designs.
  • Expertise in SOC IP integration and RTL Design for performance, low area, and low power.
  • Expertise in FE production synthesis with DFT insertion.
  • Expert knowledge of ASIC design flow and netlist flow checks – Lint, CDC, Logical Equivalence.
  • Expert knowledge of UPF flow for defining power intent of chips with multiple power domains.
  • Intimate knowledge of design interfacing to PD for ECO implementation, floorplanning and timing closure.
  • Understanding of multi-clock designs, power management, reset and power sequencing.
  • Familiarity with DFT and backend related methodology and tools is a plus.


Ownership of all aspects of development design for large SOC blocks including: Internal and/or external IP integration, design of associated infrastructure components including system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, DFT, Power and Security infrastructure. Ownership of the Integration Spec for the IP and design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing-closure for the block. Ownership of chip-level blocks common to all IP’s within the chip. These may include clock controller, power management controller, trace and debug, fuse control, general purpose IO control, among many others Collaborate closely with chip architecture, design verification, methodology, physical design, DFT, and power teams to achieve the most efficient possible design. Performance power and area analysis for your design and optimize for the best solution for the overall chip Development and maintenance of methodology and flows checks for your design. Interaction with verification team to ensure appropriate validation and coverage goals are met. Ensure Security assumptions for the chip are properly implemented within the block/s Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.

Education & Experience

BSEE is required. MSEE/Ph.D is preferred.

Additional Requirements