Processor Performance Tuning, Correlation, Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. In this highly visible role, you will be at the center of a chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- The ideal candidate should have 2+ years of performance modeling, processor verification or RTL design experience.
- In-depth knowledge of digital logic design, CPU architecture and microarchitecture
- Experience in performance modeling for advanced CPU designs
- Experience in developing performance test plans and writing/debugging assembly
- tests for performance correlation and verification
- Good programming skills in Assembly, C/C++, Verilog, System Verilog, and scripting
- Experience in silicon validation is a plus.
- Should be a team player with excellent communication skills, able to work independently on the owned unit.
As a chip performance engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: • Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models. • Work closely with software and application developers on identifying performance bottlenecks and tuning the software. • Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification. • Improve and maintain the architectural performance models. • Develop tests in assembly, C/C++, or vectors to debug and correlate the RTL and performance model. • Develop C or Verilog-based checkers for verifying the performance features. • Develop coverage monitors and analyze coverage to ensure all performance features are covered.
Education & Experience