RFIC Layout Automation Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200103379
Do you thrive on pushing the limit of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you like to innovate and improve RF layout methodologies for highly integrated RF circuits? Do you enjoy automating tedious and repetitive layout tasks with clever scripts and shortcuts? As an RFIC automation engineer, you will get to solve interesting challenges we face daily, be part of very talented RFIC design and layout teams, and contribute to Apple’s wireless success. By joining us, you will help us innovate and design products that will continually outperform previous iterations and improve the product experience for our customers across the world.

Key Qualifications

  • Extensive working knowledge of Cadence Virtuoso and Mentor Calibre is key to success.
  • We'd like you to have 5+ years hands-on experience in Skill; Python, Perl, plus other layout scripting for automation and improvements will be a bonus.
  • You also need experience in custom analog layout including floorplan, placement, routing, and verification, with exposure to deep sub-micron CMOS (16nm, 7nm, etc.). Knowledge in FinFet device structures, guard-rings, deep N-well, PN junctions, and advanced process effects such as LOD, WPE, and DFM etc. will be critical to your success.
  • Deep understanding of the trade-offs in matching, parasitic effects, high frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up. RF experience is a plus.
  • Extensive experience in verification and debugging; advanced knowledge of the tools (DRC, ERC, LVS).
  • 5+ years of experience in creating custom layout at chip, block, and device levels.
  • 5+ years with RF high frequency circuit layout experience such as LNA, Mixer, VCO, PLL.
  • We welcome a great teammate with excellent communication skills to work with multi-functional teams.


As a critical part of the layout team, you will be expected to monitor, identify, review repetitive, everyday layout tasks. You will also diagnose complex verification (DRC/LVS) and PDK issues with both Cadence and Calibre. You will collaborate with the engineering design and layout teams to understand our design concepts and constraints. After discovering the above challenges, you will draft and propose solutions to automate the everyday layout tasks. Through collaboration with our design and layout engineers to spec and finalize these automation concepts, you will utilize various programming languages to resolve the layout and design challenges; drive, review, verify, and provide detailed efficiency improvement results. We also want you to enhance and improve our layout methodology, including release flow automation, and adjusting our flow as our design kits and procedures evolve. In addition to these primary responsibilities, we also expect you to be able to layout detailed custom blocks, including the floorplan, P&R, and verification of final database for high frequency RF circuits. You will need to verify and perfect layout with simulations to meet design requirements, become familiar with our rapidly evolving flow with CAD and be ready to mentor other team members.

Education & Experience

BSEE or equivalent is a requirement, MSEE preferred

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.