DMS Modeling and Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Weekly Hours: 40
Role Number:200106773
Would you like to join Apple’s growing cellular wireless design team? Do you thrive on pushing the simulation and modeling limits of highly complex RF cellular transceivers in advanced technology nodes? Our team is responsible for all aspects of cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. As a digital mixed-signal (DMS) verification engineer, you will get to work on modeling digital and analog building blocks used in PLLs, ADCs, DACs, RF calibration blocks, and define test plans with the design team to validate the full functionality of the transceivers with all digital controls and calibrations to guarantee successful Silicon bring up without functional bugs. By joining us, your creativity and drive for continuous improvement will help us build strong methodologies and design products with high level of quality that will continuously outperform previous generations and improve the product experience for our customers across the world.

Key Qualifications

  • We want you to have 5+ years of experience and we are looking for individuals with validated experience taking chips to production. We are open to multiple experience levels.
  • Experience in analog and RF behavioral modeling and analog mixed signal simulations.
  • Solid understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, Verilog-AMS.
  • Excellent analog/RF understanding and a design background to analyze verification results.
  • Working experience in Cadence Virtuoso and ADE.
  • Hands-on experience with Analog Assertion Based Verification.
  • Experience in SystemVerilog testbench development.
  • Knowledge of UVM-AMS is a plus.
  • Understanding of analog/mixed-signal/RF blocks like VCO, A/DPLL, ADC, DAC, LNA, Mixer, VGA etc.
  • Experience in writing scripts in languages such as Perl or Python.
  • A collaborative teammate with excellent communication skills.


In this critical role, you will own the modeling and verification on digital/mixed signal designs. Job responsibilities include: - Development of RF/Analog behavioral models in Verilog or System Verilog. - Making sure that the models are accurate. - Verifying analog functions, for example, coding test scenarios and environments for analog verification and/or assertion. - Working with Analog Designers in setting up AMS simulation environment. - Supporting mixed-signal co-simulation using SystemVerilog models of analog IP.

Education & Experience

BSEE is required, MSEE/PhD in electrical engineering is a plus.

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.