Sr. CAD Engineer – Transistor level SigEM analysis flow
Santa Clara Valley (Cupertino), California, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a core team member in our advanced CAD Group, you will enhance your career working on state of the art designs, utilizing hands on experience in signal electro migration (SigEM) analysis to develop/define & refine the methodologies and flows for transistor, as well as gate level designs. The areas will include but are not limited to static and dynamic SigEM, powerEM, IR analysis and simulations, design abstract and reuse for EMIR purposes, and IP/SOC level EMIR sign-off.
- We are looking for an experienced engineer to join our team with 5-15 years of experience in EMIR field in the following areas:
- Methodology for transistor level static and dynamic SigEM analysis with spice/fastSpice simulators, model abstraction
- Model creation and reuse for transistor level designs
- In-depth knowledge in industry leading tools, like Totem/Voltus-Fi/Redhawk/Voltus/ICC-EM, etc
- PNR level EMIR analysis on different modes
- Knowledge in Extraction and STA methodology and tools
- Proficient in programming using PERL/TCL/Shell/C/C++ etc.
- Experienced with version control system, i.e. CVS, Perforce, etc.
- Layout, extraction, and simulation experience is a plus
- Experience in flow regressions is useful
- Circuit and physical design knowledge is a nice to have
- Experience with power analysis a plus
- Experience in library characterization for EMIR is helpful
Primary responsibilities include the development of custom SigEM solutions; revamping/rewriting and streamlining the EM (SigEM and powerEM) and IR flows as well as assume ownership of entire domain. You will work closely with various design groups (Custom Digital/Analog/mix-signal/Power/Technology) on their EM and IR requirements for various post layout flows. You will also work closely with vendors/foundries for tool and technology qualification and debug.
Education & Experience
MSEE or BSEE or equivalent