Sr. CAD Engineer - Signal Integrity (Noise) Analysis & Flows
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this critical role, you will be responsible for defining, implementing, and supporting the methodologies, flows, and tools necessary to ensure clean signal integrity across Apple silicon. As a CAD engineer working on signal integrity verification, you will work closely with design teams, circuit teams and CAD groups to ensure that designs meet our signal integrity and performance goals.
- The ideal candidate will have 5+ years of experience working in an EDA/CAD tool development/support role, or a design role with emphasis on back-end design closure.
- Signal integrity analysis experience with Primetime-SI, ETS/Celtic, Tempus, or equivalent.
- Solid Perl and/or TCL scripting and coding/debug skills coupled with an understanding of the design challenges in advanced technology nodes.
- Exposure to transistor-level analysis and spice simulation is a definite plus.
In this exciting role on our team, you will: - Define consistent analysis methodology, margins, and perform tool validation for signal integrity verification. - Write and support flows around core gate-level noise and static timing analysis tools. - Work closely with CAD and design teams to drive signal integrity closure efforts for multiple projects.
Education & Experience
MS or BS Degree in technical discipline.