CAD Engineer - IP QA Methodology and Applications

Austin, Texas, United States


Role Number:200113730
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a VLSI CAD methodology and applications engineer in the IP QA group, you will define, implement and support the methodology to build and verify IP collateral releases. You will be tasked to improve the quality of the releases and overall productivity of the design teams.

Key Qualifications

  • 3+ years of software development in a CAD/EDA environment
  • Strong programming background and experience with developing large software projects in a group environment
  • Self-motivated dedicated problem solver with strong communication skills
  • Proficiency in Python and/or Perl is required. Additional languages like TCL, or Javascript are a plus
  • Knowledge of version control software like GIT or Perforce
  • Knowledge of Linux and Shell scripting
  • Experience with databases is a plus
  • Familiarity with IP collateral delivered by design teams considered a plus
  • Familiarity with dependency aware flow control tools like Makefiles is useful
  • Knowledge of job scheduling systems such as NC/Accelerator or LSF a plus
  • Familiarity with EDA tools such as Crossfire, Design Compiler, Innovus, Spyglass, Verific is useful


As a member of the software development team, you will interact with teams to plan, analyze, implement and maintain scalable software solutions. Your systems will handle hard IP including standard cell and IO libraries, Memories, PDKs and design collateral from internal and external design teams and foundries. You will gain exposure to many IP views from different EDA tools/vendors and numerous design flows. You will set up Quality Assurance (QA) tests against these views using standard EDA tools. Exposure to these tools and flows will expand your knowledge to support the design team’s releases. You will organize and use databases to track metrics. Web based interfaces may be designed to visualize the data. You will be working with a small, focused, skilled and dedicated team to contribute to different CAD responsibilities as they emerge. Strong analytical skills and effective interpersonal communication are important to this position.

Education & Experience

BS or MS (preferred) in CE/EE/CS.

Additional Requirements