RF Cellular SOC Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Would you like to join Apple’s growing cellular wireless design team? Do you thrive on pushing the simulation and modeling limits of highly complex RF cellular transceivers in advanced technology nodes? Our team is responsible for all aspects of cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As an RF Cellular SOC Design Verification Engineer, you will be responsible for pre-silicon RTL verification of communication subsystem including MAC, PHY, interfaces and mixed signal digital controls for PLLs, ADCs and DACs. With deep understanding of communication systems and protocols, you will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
- We would like you to have 7+ years Wireless/Wired communication block/system verification experience.
- Advanced knowledge of SystemVerilog and DV methodology is critical to have.
- Solid verification skills in problem solving, constrained random testing, and debugging will set you up for success.
- Knowledge of RF cellular signal processing and control is a plus.
- Experience with MAC or PHY Verification is a bonus.
- Experience with SOC subsystem verification is good to have.
- Experience with SystemVerilog Assertion (SVA) would be helpful.
- We expect you to be a great teammate with excellent communication skills and the desire to take on diverse challenges.
Build block / subsystem / chip level testbench using best in class DV methodology. Build verification plans from specification and review with designers and systems engineers. Architect testbench with maximum reusability in mind, and create UVM libraries. Generate directed and constrained random tests. Debug failures, manage bug tracking, and close coverage. Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. Attend verification reviews and set standard for coding quality. Work closely with DV methodology architects to improve verification flow. Generate test vectors for silicon bring up.
Education & Experience