SoC Physical Design Engineer, Timing - STA
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions! Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this role, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.
- The ideal candidate will have 3+ years of hands-on experience in STA.
- Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
- Familiar with circuit modeling, including SPICE models and worst-case corner selection.
- Strong programming skills with Perl, TCL.
- Experience with large design STA and Timing Closure.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
- Work with design teams to understand and debug constraints, facilitate logic changes to improve timing. - Work with Physical Design team, highlighting issues and best practices. - Help create timing ECO’s for project tapeout. - Create/maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure.
Education & Experience
MSEE or equivalent is required