Analog Layout Engineer

Santa Clara Valley (Cupertino), California, United States


Weekly Hours: 40
Role Number:200116987
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually talented Analog Layout Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. We are a fast-growing and diverse group. With an employee-friendly environment. We are in charge of both all high-performance analog mixed-signal IPs and building complex chiplet levels integral to the function of Apple’s world-class products. You will become a member of a team that not only provides an environment efficient for the refinement of engineering abilities, but also promotes passion, creativity, and collaboration. Since we believe multiple perspectives and input sources are integral to innovation and invention, we highly value diversity and equal opportunities for all members. As you work with our stellar analog design team and with members of integration, CAD, and circuit- and technology- engineering, you will find our team to be a highly dynamic work environment with endless learning opportunities.

Key Qualifications

  • - Provide accurate schedules for top-level layout and integration as layout lead
  • - Meet project milestone deadlines
  • - Contribute to hierarchical planning (top down and bottom up) and integration
  • - Communicate with design engineers to negotiate any necessary layout trade-offs as needed to build complex analog layout
  • - Collaborate with off-site/on-site layout engineer
  • - Deliver high quality layout that conforms to all PDV design requirements.
  • - Recognize failure prone circuit and layout structures.
  • - Utilizing advanced CAD tools and mask design knowledge to deliver accurate and robust layout that meet stringent matching performance, area and power requirements.
  • - Running complete set of design verification tools available on block-level, Megacell level, and top-level


- 8 years of experience in RF/analog/Mixed Signal layout Design - Minimum 3 years of advanced FinFET experiences - Proficiency with Cadence Virtuoso, Calibre verification tools - Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance. - Looking for strong experience with analog DFM practices. - Experience building tight matching, low capacitance, low power analog blocks such as ADC/DAC - Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly. - Strong written and verbal communication - Relevant working experience in CAD skills such as scripting is plus

Education & Experience

Bachelors degree with 8+ years in related area of expertise

Additional Requirements