Sr. Power Integrity Engineer (PDN)

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Weekly Hours: 40
Role Number:200118526
The candidate will work within the Mac Hardware organization in the area of design and analysis for Signal Integrity and Power Integrity. This will include design simulation, enabling in situ system design performance metrics capture, enabling external I/O compliance, analysis automation of SI /PI data set metrics, correlation closure between simulation and performance metrics.

Key Qualifications

  • The candidate must have a solid technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices and trade-offs for PDN design and optimization.
  • In particular, Candidate is also required to have a good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration careabouts.
  • Good working knowledge in 3D/2D EM simulation tools, electromagnetic modeling and transmission line theory is required.
  • Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex)is required.
  • Relevant working knowledge of HSPICE, Spectre, AMS, and Simplis models for system-level transient droop analysis is also necessary.
  • Experience in CPM (Chip-Power-Model) usage for system transient analysis is an added benefit.
  • In this role, the candidate is expected to have understanding of die-package-board power delivery network co-design constraints and tradeoffs.

Description

- The candidate is expected to work with Silicon, PMU, and System Power Architecture Team to validate architectural implementation targets, and perform necessary pre-layout and post-layout analysis for guidance convergence of design solution space for target system implementation and suggest. - The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. - Ability to execute on target impedance analysis, transient voltage droop and phase margin/stability analysis is required. - The candidate is also expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. - The candidates is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. - The role includes the PI support through the specific project design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. - Experience with PERL and other scripting languages is desired. MatLab Experience is a plus. - Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required. - Candidate is also expected to have demonstrated experience in driving initiatives that improved process, procedures, and result quality.

Education & Experience

10 years experience in tool development for electrical design, MSEE with 10 years experience or PhD with minimum of 5 years experience

Additional Requirements