Sr. Signal Integrity Engineer - (Margin analysis and Compliance automation)

Santa Clara Valley (Cupertino), California, United States


Weekly Hours: 40
Role Number: 200118526
The candidate will work within the Mac Hardware organization in the area of design and analysis for Signal Integrity and Power Integrity. This will include design simulation, enabling in situ system design performance metrics capture, enabling external I/O compliance, analysis automation of SI /PI data set metrics, correlation closure between simulation and performance metrics.

Key Qualifications

  • The candidate must have familiarity and demonstrated expertise in SI simulation process for serdes links including Spice, AMI, statistical methods and demonstrated ability to automate such process steps to include leverage of commercial solvers for SI and PI as applicable. Familiarity with processing S-parameters and transform methods from frequency domain to time domain step responses is required. Fluent understanding of interconnect modeling methods, using S-parameter, W-elements, etc is required. Specific PI support includes PDN responses, transient load response, equivalent DCR and ESL extraction. Further skills required include ability to execute and author code to support DoE analysis of candidate designs and hardware variants. The candidate should be familiar with compliance process for standard interfaces and be adept at automation process for PHY compliance closure.
  • The candidate shall have demonstrated skill and working knowledge in scripting, programming expertise in C, C++, Python, PERL, and BASH/CSH; Git; Windows/Linux/Unix; SKILL (cadence) and Matlab. Demonstrated abilities in OO programming, inheritance, polymorphism, data-typing; multi-dim arrays, dictionaries; regular expressions is required. Experience with batch (non-GUI) processing support of the analysis suite is required.
  • The candidate is expected to have a deep understanding and working knowledge of SerDes IPs and its functional blocks, as well experience of register programming for configuring SerDes PHY and Controller blocks for system integration and validation needs. This also includes ability to develop scripts to engage with and use on-chip diagnostic capabilities for testing SI on high speed serial interfaces.
  • Ability to contribute in a team setting. Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required. The candidate should have experience in creating initiatives that improved process, procedures, and result quality.


The position includes design and analysis in electrical system development process across signaling and power domains. The roll includes automation of analysis and design in system SI and PI efforts across the full range of the product development process. Teamwork includes coordination with peers, system design SI/PI, hardware validation, and project EE engineering teams.

Education & Experience

MSEE or PHD, 10 years experience in system or device design and analysis.

Additional Requirements