Cellular Baseband Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems: crafting highly reusable premier UVM test benches; implementing effective coverage driven and directed test cases working with cross functional teams; deploying new tools and methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world. Do you want to have an impact on every single Apple product? As a Design Verification Engineer in this team, you are at the center of the verification effort within a silicon design group responsible for designing and productizing state-of-the-art cellular baseband modems targeted for SOCs. You are responsible for high quality verification of different levels of designs within baseband modems by working closely with cross-functional teams. You are expected to adapt to evolving requirements and do detailed test planning, and develop re-usable verification environments to achieve quality goals.
- Strong knowledge of System Verilog and UVM
- Good understanding of System C, C/C++, Python/perl
- Experience in developing and establishing DV Methodologies
- Ability to develop System Verilog Testbench with UVM methodology from scratch
- Experience in C/C++ modeling for design verification is a plus
- Experience with constraint random testing, SVA, Coverage driven verification
- Good test planning and problem-solving skills
- Knowledge of 4G/5G cellular physical layer operation (3GPP) is a plus
- Experience with verification of embedded processor cores
- Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment
- Should be a standout colleague with excellent communication and analytic and the desire to take on diverse challenges.
• Understand details of cellular modem design data and control path components and any associated system reference models • Construct detailed test plan for various components of the design including use cases, through collaborative work with cross-functional teams. • Create coverage driven verification plans from specifications, review with cross-functional teams and refine to achieve coverage targets. • Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. • Work closely with DV methodology architects to improve verification flow. • Execute test plan from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions, report verification progress against test plan and coverage metrics.
Education & Experience
BS/MS in EE/CS with at least 2+ years of dedicated/hands-on ASIC DV experience in reusable verification methodology such as UVM or OVM.