Design and Integration Engineer

Santa Clara Valley (Cupertino), California, United States


Weekly Hours: 40
Role Number:200139344
process integration experience to join the PPO Engineering team. This position requires a creative individual with a strong technical background in a relevant technical field including display or semiconductor layout, simulation, integration, and fabrication. Display and/or semiconductor processing knowledge are a must. A successful candidate will execute design projects independently from design to fabrication/integration and test.

Key Qualifications

  • Strong, direct experience in display or semiconductor layout (ex. Virtuoso, Laker, L-edit) Familiarity with parasitic extraction and panel modeling
  • Fabrication, integration, and process development
  • Familiarity with integrated circuit design such that the engineer is able to perform layout design
  • Demonstrated history of innovation for new device design concepts.
  • Direct experience in clean room environment/lab
  • A working understanding of high-volume manufacturing processes


Integrate new designs and processes to enable next generation display designs working with, testing, failure analysis, manufacturing teams, and vendors. Design and execute experiments with downstream cross-functional teams including device, architecture, optics, touch, and module to develop state-of-the art panel designs for next generation displays. Support layout and simulation for new panel designs. Characterize final samples to meet electrical, optical, yield, and reliability requirements and perform electrical measurements and analytical characterization.

Education & Experience

Ph.D. (or equivalent experience) in Electrical Engineering, Physics, Mechanical Engineering, or equivalent

Additional Requirements