Silicon Validation Engineer
Santa Clara Valley (Cupertino), California, United States
As a Silicon Validation Engineer, you will be part of the Silicon team, developing high performance Silicon. You will be a key member of the silicon validation team responsible for ensuring that we deliver high-quality silicon to customers. As part of this role, you will plan, write and execute tests to establish functional health of our ASICs, both under nominal and PVT conditions. You will lead the laboratory debug of failures with cross-functional teams (Silicon, Boards, Software, Manufacturing). You will measure and optimize performance of silicon, enabling consistent and compelling use-cases in our products.
- Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
- Strong technical background in FPGA prototype emulation, and debug
- Strong technical background in silicon validation, failure analysis and debug
- Design with RTL coding in Verilog is a must
- Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART
- Prior hands-on automation script development and optimization (using C, Python).
- Well versed in the usage of advanced lab equipment (scopes, BERTs, programmable power supplies, etc).
- Proven analytical and problem-solving abilities
- Knowledge and experience in embedded firmware development is big plus
- Good understanding of embedded firmware/software development process is a plus
- Knowledge and experience in JTAG
• Develop and execute comprehensive validation plans for our custom silicon. • Develop automation software and scripts for measurement data collection and analysis. • Drive the debug and resolution of engineering issues between cross-functional teams.
Education & Experience
• MS EE/CE with 5+ years of digital ASIC design and validation experience