CPU Processor Emulation and FPGA Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! As a Processor Emulation and FPGA Engineer in our CPU engineering team, you'll be responsible for emulation, modeling and stress testing of our CPU designs. The primary skills required for this job are RTL design, simulation, expertise in mapping designs to emulation, improving model performance, excellent communication skills, and ability to work in a fast-paced exciting environment.
- 5+ years experience in silicon design and emulation
- Hardware Emulation Platforms and tools (EVE, Palladium, Veloce, and/or HAPS)
- RTL development
- VHDL, Verilog, System Verilog (DPI and transactors)
- Simulation acceleration knowledge and FPGA prototyping
- Gate-level understanding of RTL and Synthesis
- Logic simulation: VCS, NCSIM/Verilog
- Programming/scripting skills (C, C++, Perl)
- Software Debug tools (e.g. gdb)
In this highly visible and interactive role, your primary responsibilities will be: • Create emulation models from RTL • Regress stress test on emulation and FPGA systems • Debug test failures on emulation and FPGA systems • Optimize models to be effectively executed on emulation and FPGA systems • Release models and support any issues
Education & Experience
BS or MS in Computer Engineering, Electrical Engineering or Computer Science is required.