CPU Gate Level Synthesis/Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Apple’s Silicon Engineering Group (SEG) is looking for a hardworking engineer for CPU gate level verification. In this role, the candidate would be part of Apple’s industry-leading CPU design team, working in a multi-functional role to design verification flows and ensure that our CPUs meet the highest standards for functional verification. We are looking for the person who loves working on challenges that no one has solved for and to be part of a team that is transforming silicon technology. Join us to help deliver the next groundbreaking Apple product. At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.
- The ideal candidate should possess 5+ years of CPU implementation and verification experience.
- Deep knowledge of RTL-to-gate formal verification tools (LEC) and debug techniques, low power structural verification tools (VCLP) and gate simulation and X-propagation debug (Xcelium).
- Working knowledge of Synthesis tools and flows and Perl and TCL scripting.
You will own the gate level verification of Apple’s high-performance CPU projects. Responsibilities include, but are not limited to: •Running top level formal verification, structural gate checks, low power checks, and gate level simulations. •Supporting design team in block level verification runs and debug. •Running synthesis on the RTL to find potential gate-level issues early, and providing feedback to the appropriate teams. •Creating scripts to automate synthesis and verification runs, and track the results of our various verification checks. •Working with the CAD team to further develop and enhance our verification flows.
Education & Experience
BS or MS in Computer Engineering, Electrical Engineering or Computer Science is required.