SerDes Circuit Design Engineer
Melbourne, Florida, United States
Apple Silicon Engineering is seeking qualified SERDES designers to work on the next generation SERDES PHYs for Apple’s world-leading systems-on-chip (SOCs). You will be part of a growing analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes! At Apple, we strive to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and talented Design Verification Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day! Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
- You should have experience in high-speed serial links with expertise in the following:
- Deep knowledge in high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.).
- Strong understanding of analog CMOS designs and topologies.
- Deep experience with Tx & Rx equalization techniques and circuits.
- Significant experience with high speed digital circuit (e.g., serializer, de-serializer, counters, dividers, etc.) design, analysis and verification (e.g., STA, formal verification).
- Deep experience in analyzing link jitter budget for high-speed serial links and crafting block level requirements.
- Significant knowledge of different CDR architectures.
- Experience in lab testing of high-speed serial links and defining equipment needs.
Ownership of analog and digital circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.). Work well with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.). Craft block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. Work closely with mask design to implement layout view of designs. Generation/QA of various IP Kit views/files for release to IP consumers. Defining production/bench-level test plans. Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.
Education & Experience
Master’s degree with 7 years experience or PhD with 5 years experience