Extraction CAD Engineer
Santa Clara Valley (Cupertino), California, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a team member in our advanced EDA CAD Group, you will improve your career by working on state of the art design technology. You'll have the opportunity to utilize your parasitic extraction experience to develop/define&refine extraction and simulation methodologies for transistor and gate level designs. The areas will include but not limited to capacitance modeling, interconnect parasitic extraction, RC reduction, validation of RC results in field solver etc.
- We are looking for strong engineers with 5+ years of industry experience in parasitic extraction.
- Device extraction as well as Capacitance Extraction experience.
- Good understanding of LVS flows using Calibre/ICV and LVS interface related to extraction
- Extraction flow development using StarRC/QRC/xRC for transistor level(GDS) as gate level flows(LEF/DEF)
- Programming skills in any of the following languages: Skill, TCL, PERL, Python or C/C++
- Experience in the following areas would be a plus: Field solver packages. RC reduction tools.
Responsibilities include: - Development of custom extraction solutions at the gate level and/or transistor level. - Utilizing your hands-on skills to revamp/rewrite and streamline the extraction flow. - Assume ownership of entire extraction flow, working closely with various design groups. (Full-Chip/Custom Digital/Analog) on their extraction requirements for various post layout flows.
Education & Experience
MS/BS Degree in Electrical Engineering, Computer Science or equivalent.