Santa Clara Valley (Cupertino), California, United States
Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world! Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for digital design QA Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact delivering high quality products to market quickly.
- We are looking for applicants with 1~2 years of experience in SRAM or Standard Cell Library development, EDA automation or Quality Assurance.
- Proficient in scripting in Perl, Python and/or TCL.
- Good understanding of transistor level design, SRAM and/or Standard cell circuits, cell characterization and library validation
- Experience with various EDA tools for synthesis, place-route, verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
- Familiarity of Verilog syntax, liberty models and variation format
- Knowledge of timing, power, noise and IR analysis.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a QA Engineer for the digital circuits team, you will perform the following: - Define and develop QA checks to verify EDA views of megacells and standard cell libraries - Debug and provide quick solutions for digital IP designers and/or users - Engage with CAD team to implement new automation flows and QA checks. - Work with foundries on library releases, technical support and model enhancement.
Education & Experience
BSEE/MSEE is required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.