SoC Memory Subsystem Validation Engineering Program Manager

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200153917
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Come to Apple and be at the center of the action on new custom silicon product development for Apple's groundbreaking products. As a Memory Subsystem Validation and Debug Program Manager, you will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. Your charter will include handling bring-up, validation, and the complicated debug of our state-of-the-art memory subsystem. In this wide-ranging role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these advanced memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.

Key Qualifications

  • Requires 10+ years total experience in SOC/VLSI/Memory Chip Design, Validation, and Architecture.
  • 5+ years of Technical program management, or a lead validation and debug role.
  • Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management
  • Knowledge of high performance memory subsystem, including SoC memory architecture, advanced DDR controller, PHY design and high speed IO interface, DRAM device, and associated calibration/training mechanisms.
  • Excellent debugging skills. Proven ability to drive resolution of critical problems, while under pressure.
  • Ability to understand complex technical discussions and extract action plans.
  • Ability to succinctly summarize complex details for executive reporting
  • Extraordinary leadership skills and ability to inspire team members with an innate ability to see the bigger picture.
  • Passionate to own/drive project development using well-defined metrics.
  • Phenomenal leadership and interpersonal skills with a reciprocal mindset.
  • Thrives in dynamic schedule driven development environment.
  • Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus.

Description

• Work on a high performing EPM team responsible for driving technical issue resolution to enable on-time silicon to meet aggressive product schedules. • Make detailed program level plans for memory feature roll-out and align cross-functional teams on the support and validation plans. • Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware & Software. • Drive debug activities in post silicon environments, root-cause problems, and steer the team to the best corrective action to move forward. • Focused issue reporting, bug tracking, organizing and reporting of program risks and status at an executive level. • Drive internal program process to guarantee high quality silicon execution.

Education & Experience

MS / BS Degree in Computer / Electrical Engineering

Additional Requirements