ASIC DDR/DRAM Controller Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Does making the next great technology product excite you? Imagine what you could do here! At Apple, our new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. The SoC Performance Verification is a critical job within Apple's Hardware Technology. Join this group and be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices.
- Skilled in aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
- Knowledge of Verilog/System Verilog, digital simulation and debug.
- Knowledge of DRAM memory controller architecture, including LPDDR protocols
- Knowledge of LPDDR training sequences.
- Ability to work independently to deliver the project goals.
- Exposure to UVM is desired.
- Experience with C/C++, assembly is a plus.
- Experience with perl, python or similar scripting language.
- Excellent interpersonal skills and the dream to take on diverse challenges.
As part of a very hardworking team you will be at the heart of the chip design effort collaborating with all fields (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the performance, latency and bandwidth goals of the memory controller design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. It's required that you communicate and collaborate with design, architecture, dram product engineers and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.
Education & Experience
BSEE or BSCS required, Master’s or PhD desired.