Low Power Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Does making the next great technology product excite you? Imagine what you could do here! At Apple, our new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. The SoC Low Power Design Verification is a critical job within Apple's Hardware Technology. Join this group and be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices.
- Skilled in aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
- Knowledge of Verilog/System Verilog, digital simulation and debug.
- Knowledge of computer architecture and digital design fundamentals.
- Exposure to low power verification and low power design principles is desired.
- Experience with IEE-1801 (UPF) or CPF based digital simulation flows is desired.
- Experience with perl, python or similar scripting language.
- Experience with C/C++, assembly is a plus.
- Excellent interpersonal skills and the dream to take on diverse challenges.
- Ability to work independently to deliver the project goals.
As part of a very hardworking team you will be at the heart of the chip design verification effort collaborating with all fields (vertical product model). You will be part of the team that is responsible for low power (LP) verification of various SOCs and guide IP teams with their low power verification flows. You will also have the opportunity to be involved in system LP verification involving multiple SOCs. You will review power related aspects of design and architecture specifications of SOCs and work closely with design & micro-architecture teams to validate these design features. A key component to the job is to understand the functional & power goals of the design and use this knowledge for design verification. You will develop test and coverage plans, as well as define our next generation LP verification methodology & test benches. The job will involve communicating and collaborating with design, architecture and software teams to understand the use cases and corner conditions and drive test cases. Additional responsibilities include running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. Are you ready to join the team and immerse yourself in technology of the future? Apply today.
Education & Experience
BSEE or BSCS required, Master’s or PhD desired.