Pixel IP Design Engineer- Low Power Design and Implementation
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices. In this highly visible role, you will be at the center of a multimedia IP design effort working with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- Experience in IP/SoC design, integration, and implementation.
- Experience in low-power design issues, tools, and methodologies, including UPF power intent specification.
- Experience with of power analysis and optimization methods.
- Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
- Experience with system design methodologies that contain multiple clock domains and power domains.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Knowledge of scripting languages like Tcl, Perl and Python.
- Experience in datapath and pixel-centric designs a plus.
- Strong collaboration skills.
- Outstanding written and verbal communication.
As an IP Design engineer you will have responsibilities spanning all aspects of multimedia IP design focusing on low power design: - Responsible for low power implementation for subsystems containing both internal and external IPs - Responsibility includes planning the low-power strategy and writing specifications; power intent-UPF implementation and verification; liaison with CAD, front-end design and physical design team for debugging VCLP violations and power intent flow issues; and working with chip power team on power estimation and analysis
Education & Experience
BSEE / MSEE is required