CPU Design Timing Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
- The ideal candidate will have 5+ years of Implementation experience on high performance CPU designs including at least one project that includes ownership of timing analysis.
- Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs.
- Deep knowledge in static timing tools and flows including how to handle multiple clock and power domains and other complex scenarios.
- Physical design knowledge of device physics and in particular aspects which impact timing (cross talk, noise, OCV, etc.).
- Prior experience owning the timing flow on a major CPU or similar project.
- Good understanding of Physical Design tools and methodology including but not limited to:
- - physically aware synthesis and place & route tools and flows
- - extraction, STA, and other analysis flows
- - physical design verification (LEC, DVS, etc.)
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. RESPONSIBILITIES INCLUDE BUT ARE NOT LIMITED TO: • Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.
Education & Experience
BSEE / MSEE is required.