CPU Processor Power Management & DFT Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! We are looking for a strong candidate to join our processor verification team focusing on Debug, Power, and Clock (DPC) & DFT verification. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly.
- The ideal candidate should meet the following requirements:
- 2+ years in DFT design or DFT verification or processor verification
- In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
- Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
- Knowledge of Verilog and experience with simulators and waveform debugging tools
- Good understanding of CPU architecture
- Experience in developing test plans, test benches and C-based transactors
- Experience with lab debug of CPUs using built-in DFT and debug features Experience with advanced verification techniques such as formal and assertions is a plus.
- A great teammate with excellent interpersonal skills and ability to work independently
As a Chip Verification Engineer, you will have the following responsibilities: • Work closely with architecture and RTL designers and DFT designers on verifying the functionality correctness of the Power Management and Clock Control logic and DFT logic • Develop test plans and test environments • Develop tests in C or PERL according to the test plans • Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered • Develop checkers or C-based transactors to verify the design • Work with silicon bringup team on developing tests that work in the emulation and FPGA environments • Write assertions and apply formal verification methods to the design
Education & Experience
BS, MS, or Ph.D. in Electrical Engineering, Computer Science, or Computer Engineering is required.