FPGA and Emulation Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200174328
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. As a member of the design verification team, you will play a key role in utilizing FPGA and Emulation for verification of mixed signal ASICs. You will be responsible for analyzing design specs, develop and implement test plans for major design blocks by generating suitable stimulus and gathering/analyzing results.

Key Qualifications

  • Typically requires a minimum of 8 years of experience with bring up, debugging and verification on FPGA
  • In depth experience with FPGA platforms: Xilinx FPGA boards, debug, performance and throughput tuning
  • Detailed knowledge of top down FPGA development process
  • Solid understanding of the tool flow from RTL to bitstream
  • Hands-on lab bring-up experience, debug, and instrument usage
  • Proven design validation skills
  • Experience in the usage of HLS in FPGA and Emulation
  • In depth experience writing SystemVerilog code
  • Experience with System Verilog verification environments including UVM
  • Experience in DSP design
  • Experience in Emulation platforms like Palladium
  • Good analytical skills
  • Knowledge of analog and RF blocks is a plus
  • Experience in analog modeling is also a plus
  • Experience in Python script is also a plus
  • Experience on GUI development is a plus
  • Experience on PCIe or USB is nice to have
  • Experience on HDMI or DisplayPort is a plus
  • Experience on video/image processing is also a plus
  • Excellent oral and written English skills


You will port ongoing mixed signal ASIC design to FPGA or Emulation platform. You will conduct design and verification using Verilog/System Verilog. You will develop synthesizable models for analog and RF portion. You will perform FPGA Synthesis, Place & Route, timing optimizations. You will perform bring-up, debug, and validation of designs to achieve functional and performance goals. You will build and execute plans to bring-up, debug, and validate designs. You will thoroughly document and support each of the above steps.

Education & Experience

BSEE, MSEE with industry experience over 8 years

Additional Requirements