Senior SerDes System Validation Engineer
Santa Clara Valley (Cupertino), California, United States
In this highly visible role, you will actively work within Analog-Mixed/Signal design team and participate in validation and debug of embedded circuits; collaborating with many subject areas to enable the world’s premiere products. You will closely work with a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency! At Apple, we work every single day to craft products that enrich people’s lives. And in doing so face great challenges as SOC/PHY design complexity continues to increase. If you have strong fundamentals and a track record of tackling technical challenges. If you are inspired by your curiosity and eagerness to learn new skills and to improve the value and impact of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems. If you love working with people and teams with multifaceted strengths to accomplish great things. If you like fire-fighting when challenges occur while keeping a phenomenal team spirit. If you care about society and have demonstrated leadership skills through dedication to great causes. We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high speed serial links. As a member of our dynamic team, you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers every day! And all of this while enjoying a great culture where you own your career.
- The ideal candidate should have experience in high-speed serial links with expertise in the following:
- Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.)
- Deep knowledge in system bring-up of high-speed serial links, lab testing, and defining equipment needs
- Strong knowledge in scripting (e.g. python, C, Matlab) for automation of validation efforts. Experience with system level S/W setup is a plus
- Experience in mixed-signal circuit pre-silicon verification and ability to collaborate with the circuit design team
- Knowledge of DFT to aid in the system validation
- Experience with PCB design and specifications
- Experience in leading mixed-signal SerDes system validation
- Experience with silicon bring-up, debug and production ramp
- Knowledge of SerDes design and architecture including CDR and equalization
- Knowledge of with Tx/Rx equalization techniques and adaptation
- Knowledge of link jitter budget for high-speed serial links and key block level requirements
- Knowledge of ADC based links and equalization techniques
- Strong communication, partnership and problem solving skills
- Proven track record of delivering under difficult debug and validation scenarios
- EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
- Able to think outside of the box and come up with creative solutions for system validation
- Knowledge of system level considerations e.g. ESD requirements
IN THIS ROLE, THE KEY RESPONSIBILITIES ARE THE FOLLOWING: Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system. Work with design teams to understand the architecture and define DFT needs to help improve testability and first time silicon success. Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.
Education & Experience
MSEE with 10+ years relevant experience or PhD with 7+ years relevant experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.