CPU Transactor and Testbench Development Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines with a critical impact on getting functional products to millions of customers quickly.
- The ideal candidate should have 2+ years of processor verification experience.
- In-depth knowledge of digital logic design and memory subsystem including caches and cache coherence protocols.
- Strong programming (C/C++, Verilog, Scripting), Software optimization and performance enhancement skills.
- Experience in developing emulatable transactors, and unit and full chip level test benches.
- Experience in developing testplans, assertions, and developing stimulus.
- Should be a team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design.
- Experience with emulation is a plus.
• Develop memory subsystem verification environment which can be used in both simulation and emulation. • Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU and SOC features. • Develop synthesizable verification IPs that can be utilized by Apple teams worldwide. • Work closely with the CPU, SOC, and GPU RTL design teams to understand the specifications in detail for developing verification strategies for the above mentioned environment. • Verification of memory subsystem functionality including memory hierarchy, coherency, and various bus interfaces on the SOC. • Develop coverage monitors and closing the design with collecting and covering all the cases.
Education & Experience
BS, MS, or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science is required.