SoC Design Integration Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the outstanding and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team redefining hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers.
- As a Design/Integration engineer your primary responsibilities will be in designing and integrating IPs related to CPU Cores:
- - Development of micro-architecture and design specifications
- - Implementation and verification of design in RTL and taking the design through all the FE flows.
- - Integration of various IPs and ensuring design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements.
- - Work with the SoC Design, SoC Design Verification, Implementation, Software, and post-silicon teams across multiple organizations and geographies.
- - Work with CAD and Flow teams to define and improve front-end design methodologies.
The ideal candidate will have 4+proven experience in RTL design in a SoC environment: - Fluent in RTL design - Experience in IP integration into SoC - Familiarity with AMBA Bus Protocols; familiarity ARM Cores a plus - Industry exposure to and knowledge of SoC design methodology, especially logic synthesis, static timing analysis, and logic equivalence checking. - Experience with system design methodologies that contain multiple clock domains. - Experience in clock, power management and system debug designs a plus. - Experience in low-power design issues, tools, and methodologies including UPF power intent specification a plus - Scripting in Python, Perl or other language - Strong collaboration skills. - Outstanding written and verbal communication
Education & Experience
MSEE or BSEE Degree, or equivalent is required