VLSI Chip Design Internship
Santa Clara Valley (Cupertino), California, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance and take pride in the details of your work? At Apple, we work every day to create products that enrich people’s lives. We are looking for someone who's interested in joining our Silicon Engineering team within Hardware Technologies. You’ll help design, verify, and drive to manufacture our next-generation, high-performance, power-efficient system-on-chip (SoCs). Your work will impact Apple products and ensure they efficiently handle the rich features and evolving workloads on devices that are beloved by millions. You’ll be responsible for crafting and building the key technologies that fuel all of Apple’s devices. In some positions you will be working on design, architecture, and validation of new designs across the complex SoC ecosystem often spanning multiple sub systems. Some positions are in digital domain, analog or RF, and others are a mixture. In other various roles you will develop and support chip level physical design and flow used by multiple VLSI design projects across Apple. In this role you must have excellent CAD flow programming and algorithm development background. Knowledge of physical design CAD flow is a huge plus. Strong analytical skill, effective social communication of complex concepts, and assertive leadership skills are important to every position. As a member of our dynamic group, you will have the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.
- Knowledge of basic electrical engineering principles and chip or VLSI design concepts & tradeoffs
- Strong programming background
- Basic understanding of computer architecture
- Familiar with programming languages such as Python, Perl, C, tcl, etc.
- Self-motivated, dedicated problem solver with strong social and communication skills.
- Understanding of different aspects of physical chip design: floorplanning, placement, pin assignment, feed through insertion, clock distribution, pad ring construction, routing, and timing analysis
Provide innovative solutions to improve area, power, and performance of chip level VLSI designs Provide detailed documentation of work and communicate across teams
Education & Experience
Pursuing a BS, MS, or PhD in EE, EECS, CS, CSE, or equivalent