CPU Physical Design Optimization and Methodology Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role as a part of an industry recognized and innovative CPU design team, you will contribute to solving intriguing and key problems in the physical design (PD) and optimization space. With a steadfast focus on improving Power, Performance and Area (PPA) of CPU designs, you’ll have the opportunity to interface with most teams in CPU design and influence SOC teams as well.
- The ideal candidate should possess a BS or MS in Electrical Engineering with 5+ years of CPU PD, optimization and/or methodology experience.
- Expertise in high-performance, low-power physical design and implementation techniques with industry standard synthesis and PnR tools
- Proficiency in using STA and power analysis tools
- Proficiency in programming and scripting (Perl, TCL) with strong fundamentals
- Strong understanding of logic design (RTL) and electrical fundamentals
- Excellent communication and interpersonal skills
As a Physical Design Optimization and Methodology Engineer, you will own or participate in the following: • Develop Apple internal and drive cutting edge industry PD and optimization tools and flows for best in class PPA (including but not limited to low power and high performance physical design) • Work extensively with implementation and RTL teams to help optimize and converge their designs by removing challenging implementation roadblocks • Coordinate with and influence CAD team(s) and external tool vendors on the development of PD and optimization flows and their adoption in CPU design
Education & Experience
BSEE/MSEE is required.