Design Verification Engineer - Networking Hardware
San Diego, California, United States
Do you have a passion for invention and self-challenge? Do you grow with pushing the limits of what’s considered feasible? As a member of the team, you will be responsible for verifying complex cellular baseband modems: crafting highly reusable outstanding UVM test benches; implementing effective coverage driven and directed test cases working across different teams; deploying new tools and methodologies to improve the quality of tape-out readiness. By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! As a Design Verification Engineer, you are at the center of the verification effort within our silicon design group! You will be designing and productizing state-of-the-art baseband modems targeted for SOC. You are responsible for high-quality verification of different levels of designs within baseband modems. Expectations are to adapt to evolving requirements and do detailed test planning and develop re-usable verification environments to achieve quality goals.
- You will have at least 2+ years of dedicated/hands-on ASIC DV experience in reusable verification methodologies such as UVM or OVM.
- Strong knowledge of System Verilog and UVM
- Good understanding of System C, C/C++, Python/Perl
- Experience in developing and establishing DV Methodologies
- Ability to develop System Verilog Testbench with UVM methodology from scratch
- Experience in C/C++ modeling for design verification
- Experience with constraint random testing, SVA, Coverage driven verification
- Knowledge of 4G/5G cellular physical layer operation (3GPP) is a plus
- Experience with verification of embedded processor cores
- Hands-on verification experience of Bus Fabric, PCIe, Interconnect, NOC, AHB, AXI, based bus architectures, data path in UVM environment
- Should be a standout colleague with excellent communication and analytic skills with the desire to take on diverse challenges.
Once you understand the details of cellular modem design data and control path components and any associated system reference models. You will construct a detailed test plan for various components of the design including use cases. You will build coverage driven verification plans from specifications, review with multi-functional teams, and refine to achieve coverage targets. Architect UVM-based, reusable test benches with components for stimulus, checkers, and reference models. Work closely with DV methodology architects to improve verification flow. Execute test plan from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions, report verification progress against test plan and coverage metrics.
Education & Experience
BSEE is required. MSEE or Ph.D. is preferred.