GNSS Wireless Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Would you like to join Apple’s growing wireless silicon development team? Global Navigation Satellite Systems (GNSS) space vehicles transmit the power of a lightbulb, they are 13000 miles away, and are moving four kilometers per second. The received signals are commonly one hundred times weaker than cosmic microwave background radiation left over from the Big Bang and arrive next to interfering signals ten billion times stronger, just few MHz away. Our GNSS team is part of Apple's wireless SOC team. We are a vertically integrated engineering team spanning RF, mixed signal analog design, systems engineering, Design Verification, RTL design, firmware and software engineering, Test, and Validation. Our focus is on highly energy efficient and robust GNSS receiver design. We develop GNSS technology that touches hundreds of millions of lives, something we are passionate about. We’d like you to consider being a part of our team. As a GNSS Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of our GNSS IP and SoC subsystem. As part of our DV team, you will develop reusable testbench and verification environment deploying the latest methodology, working closely with GNSS and SoC front-end designers and Systems Engineers.
- 4+ years Wireless/DSP block/system verification experience.
- Advanced knowledge of SystemVerilog and DV methodology.
- Solid verification skills in problem solving, constrained random testing, and debugging.
- Knowledge of GNSS and SOC subsystem verification experience are desirable.
- Experience with SystemVerilog Assertion (SVA) a plus.
- Strong verbal and written communication skills are needed.
• Build block / subsystem / chip level testbench using best in class DV methodologies. • Build verification plan from specification and review with designers and systems engineers. • Architect testbench with maximum reusability in mind and create UVM libraries. • Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage. • Create and analyze block/subsystem level coverage model and add test cases to increase coverage.
Education & Experience
• A BS degree in Electrical Engineering is required; a M.Sc. degree is desirable.