Static Timing Analysis Engineer
Santa Clara Valley (Cupertino), California, United States
Do you love crafting elegant solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.
- The position requires thorough knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background:
- At least 5+ years hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and cross-talk effects on timing.
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below).
- Knowledge of timing corners/modes and process variations.
- Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs.
- Proficient in scripting languages (Tcl and Perl).
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).
- Self starter and highly motivated.
- Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.
As a Wireless ASIC STA engineer, you will be a part of the Wireless SOC digital design team responsible for providing integrated solutions for wireless chips. Responsibilities include: • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Develop and maintain methodology and flows related to timing verification and closure. • Generation of block and full chip timing constraints. • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure. • Support digital chip integration work and flows.
Education & Experience
BSEE, MSEE or equivalent experience.