Static Timing Analysis Engineer
Santa Clara Valley (Cupertino), California, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and exceptionally talented Timing Design Engineer. As a member of our dynamic group, you will have the unique and rewarding opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering best in class PHY designs. You will be directly involved in timing closure and/or physical designs of best in class PHY design.
- The ideal candidate will have 5+ years of Physical Design experience on high PHY and/or SOC designs
- Knowledge about industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
- Experience in developing and implementing STA constraints
- Solid Understanding of all aspects of Timing flow, Physical construction, Integration and Physical Verification Working Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes
- Power user of industry standard Timing ,Physical Design & Synthesis tools Solid Understanding of scripting languages such as Perl/Tcl
As a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on critical blocks by working with RTL, PD teams. Develop and validate high performance low power clock network guidelines. Perform Timing optimization and validate the design for functionality. Generate and Implement ECOs to fix timing etc. Run Timing verification flow at chip/block level and provide guidelines to fix violations to other designers and/or perform the fixes. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
Education & Experience
BSEE / MSEE is required