Custom Logic Design and STA Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200201518
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The Display and Touch Silicon (DTS) team is searching for a self-motivating engineer for the role of Custom Logic Design and STA engineer. As a member of the DTS team, we will be working on the leading-edge technology to build best-in-class custom mixed-signal designs used to connect our world-class products to the world as well as optimizing their performance. You will become part of a development team that cultivates engineering excellence, creativity, and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in this type of environment. You will work with us from Apple's headquarters in Cupertino, California. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products?

Key Qualifications

  • The ideal candidate will have minimum of 5 years of industry experience and possess the following qualifications:
  • Experience in transistor- and gate-level static timing and noise analysis.
  • Experience in transistor- and gate-level custom logic design.
  • Experience in timing / SDC constraints generation and management.
  • Experience in RTL design is a plus.
  • Experience in SRAM design is a plus.
  • Experience with NanoTime, PrimeTime, and Tempus STA tools.
  • Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with OCV / AOCVM / POCV.
  • Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
  • Proficiency in scripting languages (Tcl and Perl).
  • Familiarity with synthesis, logic equivalence, DFT, and backend related methodologies and tools.
  • Familiarity with ECO techniques and implementation is a plus.
  • Strong communication and interpersonal skills.

Description

In this role, you will perform timing analysis on custom design circuits, delivery timing views to integration teams, as well as develop custom logic designs in mixed-signal chips. You will work closely with custom design engineers, and cross-functional teams at the silicon and module levels. Responsibilities includes: • Custom design timing closure ownership throughout the entire project cycle. • Develop and implement STA constraints from specs. • Perform block- and chip-level static timing and noise analysis. • Design and characterize transistor- and gate-level custom digital circuits in mixed-signal chips. • Work with RTL and custom design teams on timing changes and propose correct-by-construction designs and methodologies. • Assist design verification and DFT team to debug functional and testing issues. • Assist CAD in developing and maintaining methodologies and flows related to timing verification and closure.

Education & Experience

Additional Requirements