IC Packaging Engineer
Santa Clara Valley (Cupertino), California, United States
Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for excellence and perfection to work towards an extraordinary result? We are looking for a hardworking, and passionate IC Packaging Engineer. In this highly visible role, you will initiate package concepts, own and drive advanced package selection, new product package structure and configuration optimization. You will be responsible for Packaging integration and package technology development for a variety of projects including SoC.
- We are looking for an individual experience in Semiconductor Packaging field.
- Someone who has working knowledge in materials characterization and analysis
- Ideal candidate will have working knowledge of Wafer Level Packaging, 2.5D packaging and 3D packaging technology.
- General understanding of packaging technologies, assembly processes, IC packaging materials, reliability standards, FA techniques, etc.
- Good communication skills that can enable the candidate to work well with internal cross functional teams and overseas suppliers.
- Ability to work independently and tackle projects with minimum supervision.
- Good engineering problem solving skills with strong engineering physics and fundamentals.
- Can use package design softwares, APD, Virtuoso, etc.
- Working knowledge in memory packaging.
- Good program management skill
Responsible to lead packaging technology development including advanced 2.5D/3D packaging. Work with cross functional team and lead SoC Package integration efforts. Package architecture / Package integration Innovation Work with foundry and OSAT to bring packaging solution from concept to HVM. Drive industry with advanced Package solutions, new material development, and specs. 5% International travel.
Education & Experience
Ph. D. M.S. or B.S. in Engineering field such as Electrical, Mechanical, Chemical, Material, Physics, etc.