Wireless ASIC Design Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200201592
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance of every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

Key Qualifications

  • 5+ years of hands-on experience in ASIC design flow
  • Proven track record of high-performance designs in high volume production for low power applications
  • Knowledge and experience in the MAC layer of wired/wireless communication system are highly desirable
  • Solid background in computer architecture including one or more of the following: Bus fabric, especially APB/AHB/AXI, Tiered memory systems, System debug architecture, Power management with multiple power domains, Integer and floating-point numeric units, High-speed data path, and control units
  • Experience in ASIC design front end flows – Lint, CDC, STA, LEC
  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus
  • SoC top-level integration experience and system architecture knowledge are a plus
  • Proficiency in scripting languages (Shell and Perl desirable, Python skills are a plus)
  • Self-starter, highly motivated, highly organized, and schedule-driven is a must
  • Excellent communication and ability to work well in a team


Writing specifications and other documents Microarchitecture definition IP integration, RTL logic design, and verification support Running front end tools to ensure lint-free and CDC/RDC clean design Synthesis and timing constraints Power analysis and optimization Collaboration with system and software team to ensure functionality, performance and power efficiency Develop and maintain methodology/flow/checks for your design

Education & Experience

BSEE required with equivalent years of experience, MSEE desired.

Additional Requirements