High Speed Analog/Mixed-Signal IC Architect/Design Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200201599
Apple products are impacting millions of people across the globe. Our mission in Analog-Mixed/Signal group is to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency. We face great challenges as SOC/PHY design complexity and the number of projects increase within short production cycles. Those great challenges are always tackled by our amazing team members who are driven and eager to learn new skills! If you have strong fundamentals and a track record of tackling technical challenges. If you are passionate about your curiosity and eagerness to learn new skills and to maximize the value and impact of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems. If you love working with people and diverse teams to accomplish great things. If you like fire-fighting when challenges occur while keeping an extraordinary team spirit. If you care about society and have demonstrated leadership skills through commitment to great causes. We are looking forward to having you join our team and help us deliver on these challenges while enjoying a great culture where you own your career.

Key Qualifications

  • Proven track record in high-speed analog/mixed-signal architecture and circuit design and productization
  • Deep understanding of PLL and clocking fundamentals and solid understanding of phase noise, jitter analysis/budgeting and loop dynamics
  • Demonstrated innovation, self-learning, leadership skills, and a growth mindset throughout your career
  • Excellent teamwork and productivity/scripting skills
  • You are expected to have a proven track record in one or many of the following:
  • Design of High speed PLL and clocking circuits: RO/LC oscillators, drivers, phase interpolators, dividers, TDC, DTC, and reference circuits
  • Design/debug RTL of algorithms and functions for Digital PLLs
  • Develop System Verilog models and perform behavioral simulations to investigate new clocking architectures’ performance and function

Description

Given your high aspirations, we expect you to apply your expertise to the development of PLL and clocking architectures and circuits for diverse applications including SoC, SerDes, CPU and Cellular applications.

Education & Experience

Requires Bachelor’s Degree with 8+ years of experience, Master’s Degree with 6+ years of experience in related areas of expertise or Ph.D. + 3 years of experience

Additional Requirements